PCBA for Lens Polishing Machine Haruchika HP-043

  • Date: 2011.
  • Owned and developed by Cisium, Inc.
  • Customers: industrial companies.
  • Creators: Raúl Bartolomé Castro and others.
  • Raúl’s contribution: project manager, engineering manager and chief engineering. Additionally, senior engineer for electronic design and firmware development.
  • Market: industrial.
  • Product category: industrial automation.

The scope of this project is an obsolete industrial machine without manufacturer support. The system automation was implemented with a full custom board, using discrete electronic components in an analog and digital electric nature. The target was to fix the machines, replacing the damaged boards with a new control system.

During the systematic analysis of the machine and solution cases, we decided to reject the utilization of standard PLC due to the reduce space for the location of the components, also we disregard the possibility to make a pure reverse engineering (just copying the PCB) because it was based on obsoletes components with difficult access to market, finally we decided to create a new PCB from scratch using the latest sate of the art technology, but implementing the same behavior than the original board.

The new control board was designed around the Xilinx CoolRunner-II CPLD XC2C64A, giving a new air to the system allowing to reprogram anytime instead of a hardwired solution. That was the strength of the new solution, smooth reconfiguration system without any issue.

The CPLD was programmed in VHDL using a state machine and schematic level to the top level connectivity. Thanks to ISE WebPACK Design Software we were able to simulate the machine and create an accurate model to the system that allows us an easy integration of the program.

Special attention we took in the design of the inputs, we keep the same noise margin in the inputs. It means, instead to create 3.3V inputs, we keep the original supply voltage of 12V for the inputs in order to have robust inputs with regards of the electrical noise. The implementation was done with comparators using hysteresis and setting the switching threshold to 6V.

Key Features

Design based on the Xilinx XC2C64A CoolRunner-II CPLD. Features:

  • Optimized for 1.8V systems
    • As fast as 4.6 ns pin-to-pin logic delays
    • As low as 15 μA quiescent current
  • Industry’s best 0.18 micron CMOS CPLD
    • Optimized architecture for effective logic synthesis
    • Multi-voltage I/O operation — 1.5V to 3.3V
  • Package 44-pin VQFP with 33 user I/Os
  • Advanced system features
    • Fastest in system programming
    • 1.8V ISP using IEEE 1532 (JTAG) interface
    • IEEE1149.1 JTAG Boundary Scan Test
    • Optional Schmitt-trigger input (per pin)
    • Two separate I/O banks
    • RealDigital 100% CMOS product term generation
    • Global signal options with macrocell control
      • Multiple global clocks with phase selection per macrocell
      • Multiple global output enables
      • Global set/reset
      • Efficient control term clocks, output enables, and set/resets for each macrocell and shared across function blocks
  • Advanced design security
  • Optional bus-hold, 3-state, or weak pullup on selected I/O pins
  • Open-drain output option for Wired-OR and LED drive
  • Optional configurable grounds on unused I/Os
  • Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
  • PLA architecture
  • Superior pinout retention
  • 100% product term routability across function block
  • Hot pluggable

All inputs with 5V noise immunity, 1V hysteresis and double capacitor filtering, using the Low Power Low Offset Voltage Quad Comparators National Semiconductors LM2901. Features:

  • Wide supply voltage range: 2 to 36 VDC or ±1 to ±18 VDC
  • Very low supply current drain (0.8 mA) — independent of supply voltage
  • Low input biasing current: 25 nA
  • Low input offset current: ±5 nA
  • Offset voltage: ±3 mV
  • Input common-mode voltage range includes GND
  • Differential input voltage range equal to the power supply voltage
  • Low output saturation voltage: 250 mV at 4 mA
  • Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems

The outputs we improved using the latest BDX53B Darlington Power Transistors from ON Semiconductor. Features:

  • High DC Current Gain − hFE = 2500 (Typ) @ IC = 4.0 Adc
  • Collector Emitter Sustaining Voltage − @ 100 mAdc
    • VCEO(sat) = 2.0 Vdc (Max) @ IC = 3.0 Adc
  • Low Collector−Emitter Saturation Voltage
    • VCE(sat) = 2.0 Vdc (Max) @ IC = 3.0 Adc
    • VCE(sat) = 4.0 Vdc (Max) @ IC = 5.0 Adc
  • Monolithic Construction with Built−In Base−Emitter Shunt Resistors
  • Pb−Free Packages

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